The present invention generally relates to frequency synthesis, and particularly relates to transceiver frequency synthesis, such as in full duplex applications with variable duplex distances.
Frequency synthesizers pose a number of design challenges. For example, in receiver frequency generation, use of fractional-N frequency synthesis can be advantageous because of the flexible choice in frequencies, frequency channel spacing, frequency hopping time, etc., afforded by such configurations. However, fractional-N frequency synthesis can increase spurious frequency noise.
Narrowing the loop bandwidth of the frequency synthesizer mitigates spurious frequency problems. Unfortunately, the narrow loop bandwidth does not complement transmit frequency signal generation, because the narrow bandwidth leaves the frequency synthesizer prone to frequency pulling problems arising from unwanted electromagnetic coupling between the synthesizer's oscillator and the relatively high-power modulated transmit signal present during active transmission. Indeed, the frequency synthesizer's resistance to frequency pulling is directly dependent on its loop bandwidth.
One approach to addressing these competing interests in full duplex applications, which require the simultaneous generation of transmit and receive frequencies, is to implement wholly separate transmitter and receiver frequency synthesizers. While such an approach does provide good flexibility in frequency generation, it still has the problem of finding loop bandwidth compromises between fractional-N divider noise suppression and frequency-pulling sensitivities, and can be expensive and large in terms of circuit board real estate. Other approaches include the use of one or more local oscillators (LOs) common to receive and transmit loops, but such architectures sometimes limit frequency flexibility and/or require significant filtering for noise reduction, etc.